ISRO is endeavouring to enter the domain of operational hyperspectral imaging from earth orbit. To find a suitable detector array for the proposed Hyperspectral Imaging Satellite’s (HySIS) payload in terms of performance and delivery schedule for meeting the project requirements, a detailed survey was conducted.
Vis-NIR Hyperspectral payload of HySIS satellite is a hyperspectral imaging sensor operating in the visible and near infrared regions of the electronmagnetic spectrum. This earth observing imaging spectrometer will operate in the 0.4 to 0.95µm spectral range, will have 55 spectral bands with 10 nanometre spectral sampling and 30 metre spatial sampling. Push-broom scanning mode is the operating mode of this sensor from a 630 km orbit.
Following the survey to find detector arrays, Vis-NIR Hyperspectral Imaging payload was originally conceptualised around a commercial off-the-shelf detector array developed by a foreign supplier. For the shortlisted detector array from that supplier, the pixel size, charge handling capacity and Signal-to-Noise ratio were not complying with the requirements.
So, these requirements were subsequently proposed to be met at the system level by employing the technique of ‘spatial and spectral signal binning’. But, following the recommendations during a prominent review, the payload team worked out a plan for indigenous development of a ‘Frame Transfer Charge Coupled Device’ (CCD 1000 X 66, 11µm x 26µm). In this regard, the Space Applications Centre (SAC) discussed the work breakdown and sharing structure with Semi Conductor Limited (SCL), Chandigarh, an autonomous body under the Department of Space, and the same was laid out between SAC and SCL team members.
As per the discussion, chip architecture (Fig.-1), device design,chip layout, and package design were carried out at SAC to meet project requirements with respect to spatial and temporal resolution, Dynamic Range, Modulation Transfer Function, Smear and spectral responsivity. 1000 X 66 pixels were designed to be readout, from both top and bottom directions, using four analog video ports to meet the frame rate requirement. Metal strapping was used for swiftly transferring integrated charges from image to storage region, in order to reduce image smear. Designs (both at chip and package levels) went through detailed review, before clearing for mask making and package fabrication, by a team consisting of members from SCL and SAC.
Wafer processing was completed at SCL with top priority. During wafer processing at SCL, the SAC team developed a test bench (Hardware, Firmware, and software for providing electro-optical stimuli) for electro-optical evaluation of the chip. Wafer level testing, assembly and packagingwere carried out at SCL. Few dies were packaged (Chip-on-board) at SCL for functionality verification.
The Chip on Board (COB) packages have successfully gone through functionality verification checks at SAC. Fig.-2, 3 and 4 are images of COB, test setup electronics, and EO test bench respectively. Raw images generated under normal laboratory illumination conditions at F#2, a focal length of 105mm, and an integration time of 30 milliseconds and acquired by the chip, are given in Fig.-5A through 5D.